1. Field of the Invention
The present invention relates to a memory device, and more particularly, a method for controlling a sense amplifier driver of a memory device.
2. Background of the Related Art
A sense amplifier detects a voltage or current level of an input signal as a threshold value and amplifies the input signal. The sense amplifier may also detect only an input signal of a specific temporal area. The sense amplifier serves to accurately sense and amplify data stored in a memory, and then transfer the amplified value to other circuits. For integrated circuits, the sense amplifier requires high sensitivity, high speed operation, wide operation range of power source voltage, low power consumption and small area layout.
FIG. 1 is a block diagram of a related art memory device using a sense amplifier. As shown in FIG. 1, the related art memory device includes an address generator 10 for generating addresses, and a pre-decoder 20 for decoding the addresses generated by the address generator 10. A word/bit line decoder 30 decodes and selects corresponding word line and bit line based on an address decoding signal generated by the pre-decoder 20. A memory cell in a memory array 40 is accessed based on the selected word line WL driven by the word/bit line decoder 30.
Since the data sensing speed of the sensing amplifier 50 serves to determine access speed of the memory device, a sense amplifier driver is provided per sense amplifier or more to increase the data sensing speed. A sense amplifier 50 receives data accessed from the selected memory cell of the array 40 through the bit line BL and amplifies the data. An output latch 60 latches a signal provided from the sense amplifier 50 in response to an address transition detecting (ATD) signal generated by the address generator 10.
FIG. 2 is a circuit diagram of the related sense amplifier driver. A first PMOS transistor P10 includes a drain terminal connected to a supply terminal of a pull-up control signal SPC of the sense amplifier and a source terminal receiving an external voltage, and is turned on/off by a first driving signal SP1 provided at a gate terminal. A second PMOS transistor P11 includes a drain terminal connected to the drain terminal of the first PMOS transistor P10 and a source terminal receiving an internal voltage, and is turned on/off by a second driving signal SP2 provided at a gate terminal.
A first NMOS transistor N12 includes a drain terminal connected to a supply terminal of a pull-down control signal SNC of the sense amplifier and a source terminal connected to a ground terminal, and is turned on/off by a third driving signal SN1 provided at a gate terminal. A second NMOS transistor N13 includes a drain terminal connected to the drain terminal of the first NMOS transistor N12 and the source terminal connected to the ground terminal, and is turned on/off by a fourth driving signal SN2 provided at a gate terminal. A bit line equalizer circuit (BLEQ) 100 is turned on by a bit line equalizer signal BLEQ provided to equalize levels of the pull-up control signal SPC and the pull-down control signal SNC when the sense amplifier is not operated, and electrically connects the pull-up control signal SPC with the pull-down control signal SNC.
FIG. 3 is a circuit diagram of a related sense amplifier, and FIG. 4 shows signal waveforms provided by each element of FIGS. 2 and 3. Referring to FIGS. 3 and 4, to completely transfer data of the memory cell to the sense amplifier before enabling the word line WL, a signal selected among block selection (BS) signals precharged to VDD level ascends to VPP level and a signal not selected among the block selection signals descends to VSS level (See waveforms of BSI/BSJ(Block selection I/Block selection J)).
Thereafter, charge sharing occurs as the word line WL is enabled. To completely develop the sensed data, the bit line BL is completely developed by the pull-up control signal SPC and the pull-down control signal SNC of the sense amplifier.
At this time, if the pull-up control signal SPC is supplied by only the internal voltage, the bit line loading is too large (because BSI/BSJ are VPP level), thereby causing the first developing time to be long. To improve this problem, the related art adopts the external power source as shown in the waveforms WL, SP1 and SP2 of FIG. 4.
In other words, to avoid the extended development time due to large bit line loading, the external voltage, i.e., the SP1 signal is developed together with the internal voltage for a specific pulse width. Thus, overdriving occurs to improve the first developing time. In the waveform diagram, the label SBL/SBLb are the bit lines in the sense amplifier and CBL/CBLb are the bit lines in the cell.
The related art method for controlling the sensing amplifier driver has various problems. For example, the developing time of the first data has been improved using the internal voltage and the external voltage during the first development, as shown in the signal waveform of the SPC. However, overcurrent may flow from the supply terminal of the internal voltage to the supply terminal of the external voltage during a specific pulse width, so that reliability of the sense amplifier is deteriorated. In addition, since the external voltage and the internal voltage are conducted together, a short may occur in a core of the memory device. Further, since an area for applying the external voltage is required, the packing density of the memory device which adopts such a sense amplifier is deteriorated.